With rapid advances in semiconductor manufacturing technology, semiconductor devices are moving in the direction to have a higher component density and higher level of integration degree. As one of the most basic components of semiconductor devices, transistors are widely used. Meanwhile, the length of the gate of a transistor has become much smaller. However, a smaller gate length can often cause a short-channel effect in the transistor, and can further cause leakage current. As a result, performance of the transistors can be degraded.
Currently, performance of transistor is improved by increasing carrier mobility. When the carrier mobility is increased, the drive current of the transistor can be increased accordingly, and the leakage current can be suppressed. Since a key element to increase the carrier mobility is to increase the stress in the channel region of the transistor, the performance of the transistor can be improved by increasing the stress in the channel region.
A conventional method for improving the stress in the channel region of the transistor includes forming a stress layer in the source region and in the drain region. For example, the stress layer in a PMOS transistor can be made of SiGe. Since SiGe and Si have the same crystal structure (e.g. a “diamond” structure), SiGe can be grown directly on Si. Because the lattice constant of SiGe is greater than the lattice constant of Si at room temperature, lattice mismatch can be generated between the epitaxial SiGe and the Si. The SiGe stress layer can thus exert compressive stress to the channel region of the transistor. Accordingly, carrier mobility in the channel region of the PMOS transistor can be improved.
Similarly, the stress layer of a conventional NMOS can be made of SiC. At room temperature, the lattice constant of SiC is smaller than the lattice constant of Si, and lattice mismatch can be generated between Si and the epitaxial SiC. The SiC stress layer can thus exert tensile stress to the channel region of the NMOS transistor. Carrier mobility in the channel region of the NMOS transistor can be improved.
However, transistors having stress layers often have undesirable morphology and unstable electrical properties.